In the processing of semiconductor devices, dielectric isolation is increasingly used rather than junction isolation for increasing the packing density of resultant structures and for providing physical separation of dissimilar devices. Moreover, trench isolation is used, particularly with planarization techniques such as chemical-mechanical polishing (CMP), to provide for a small, yet very electrically effective dielectric isolation region, and yet still affords a planar structure for facilitating subsequent formation of fine-pitch interconnect lines.
Frequently, tetra-ethyl-ortho-silicate (TEOS) is the dielectric material used to fill a trench previously etched into the surface of the substrate, and the surface of the TEOS trench is planarized with the silicon substrate surface by chemical-mechanical polishing.
Referring to FIG. 1A, two trench isolation regions 102 are shown formed within a semiconductor substrate 100. An active area 103 (for later formation of a device, such as a field effect transistor) is shown located between the two trench isolation regions 102. The surfaces (labeled as 105) of the trench isolation regions 102 are shown as having been planarized with the surface (labeled as 104) of the active area 103, as is well known in the art of trench formation.
The various etches used to clean the silicon surface in the active areas (such as active area surface 104) are also usually applied to the trench isolation region surface 105. Because the etch rate of common trench fill materials, such as TEOS, is frequently greater than the etch rate of various substrate materials (such as single crystal silicon), a significant over-etching of the trench regions 102 occurs. This over-etching creates a recessed trench fill surface 106, as shown in FIG. 1B, which leads to degraded electrical performance of the dielectric isolation provided by the trench. Such degraded performance includes increased leakage currents along the edges of the recessed TEOS trench.
An improved method of trench isolation formation includes applying a polysilicon layer above a planarized trench, and converting the polysilicon to oxide prior to etching the active areas. This converted oxide is denser than the materials usually used to fill the trench, such as TEOS, and results in less over-etching of the trench isolation region. The quality of the dielectric isolation is consequently improved, and in particular, less leakage current flows across the trench isolation region. Moreover, less leakage current flows from a subsequently formed local interconnect layer.
In one embodiment of the present invention, a method of forming an integrated circuit structure upon a semiconductor substrate having a top surface includes forming a plurality of trench isolation regions, each filled with a trench dielectric material, at the top surface of the semiconductor substrate, the trench isolation regions defining active area regions therebetween; forming a protective layer over and fully covering the trench isolation regions; and then removing material overlying the active area regions to expose the top surface of the semiconductor substrate within the active area regions; wherein the protective layer remains over the trench isolation regions during at least a portion of the removing step to protect the trench isolation regions and to reduce removal of trench dielectric material during the removing step; and then forming a gate dielectric layer on the exposed top surface within the active area regions; and forming a gate electrode over the gate dielectric layer within an active area region.